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Jesteś gościem nr:
532399
   

Szczegóły artykułu:

Wydawnictwo: Academic Journals Poznan University of Technology

Numer: 95/2018 Str: 57


Autorzy: Pavel Pavlasek, Miroslav Pavelek, Branislav Bobrucky, Matej Mrazik


Tytuł: DESIGN AND VERIFICATION OF THE CHIP THERMAL MODEL: THE ASSESSMENT OF A POWER MODULES RESISTANCE TO HIGH CURRENT PEAKS


Streszczenie: The paper is focused on creating a thermal model which provides information about the thermal conditions in the semiconductor devices. Increasing the current density and pressure on prices make the optimization of thermal systems an important part in the design process. Simulation analysis has become with development of computer technology an excellent equipment to achieve it. In creating the model, we take account of material and geometric parameters of bonded chips. By the simulation we obtain the necessary information about the components and thermal stresses, these results can be applied in the device design procedure and technology of production. Resistance to bonded diodes is determined by chip parameters and bonding parameters such as the number of bundles, their spacing, and material. Resistance in practice is determined by experimen-tally measuring IFSM, a peak permeable, unrepeatable current. Also, in the work we analysed voltage-current VA characteristics of power diodes suc


Słowa kluczowe: power modules, thermal model, simulation, finite element method.


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